Stockhouse

Fujitsu Develops Clock Distribution Circuit for High-Speed, Low-Power Data Transmission between CPUs

Fujitsu Develops Clock Distribution Circuit for High-Speed, Low-Power Data Transmission between CPUs Contributes to the next generation of higher performance servers and supercomputers through a 20% ...
Design-Reuse

Optimizing clock tree distribution in SoCs with multiple clock sinks

In the design of high-performance high-speed integrated circuits, clock tree organization is fundamental to distribution of e-clock signals to the whole area of an integrated circuit or to a ...
EDN

LTC Design Note: Robust 10MHz reference clock input protection circuit and distributor for RF systems

RF instruments and wireless transceivers often feature an input for an external reference clock, such as the ubiquitous 10MHz reference input port found on RF instruments. Many of these same systems ...
Electronic Design

Understand, Measure, And Optimize Clock Distribution Additive Jitter To Achieve Best Performance

High-speed communications require system designers to optimize clocking performance while adhering to both performance and cost-budget requirements. When selecting an optimal clock, the developer must ...
EDN

Clock technique resonates for nixing jitter

Portland, Ore. – Details about a resonant clock distribution circuit jointly developed by IBM Corp. and Columbia University will be revealed at the IEEE's International Solid-State Circuits Conference ...
Design-Reuse

Lattice Releases Development Platform for SERDES and Video Clock Distribution

HILLSBORO, OR -- Dec 14, 2009-- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of a $169 evaluation board for the ispClock(TM) 5400D programmable clock ...
Electronic Design

Clock Generators Bring Stability to Timing-Circuit Designs

Clock speed is equivalent to data movement in applications that receive and process hundreds of megabytes of data each second. Applications involved in moving enormous volumes of data include cellular ...
Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.